comp logic


1.


		   Vin

		   |
		   |
		+----+
		|    |
    Actv    ----|    |---- Vout
		+----+


if actv > 0.7V

	
	if Vin = +Ve

		Vout = +ve

	if Vin = -Ve

		Vout = -ve or floating (check)
	

else
	Vout = floating



any line that could be floating should be tied to +ve or -ve by a resistor,

	or ensure that the level is never used as an input when this is the case

	(e.g. 100K resistor from that line to the +ve or -ve line)






2.


And

		    |
		--- X ---+
			 |
			 |
	 	    |	 |
		--- X ---X --- output

Or


		    |
		--- X --+
			|
			|
	 	    |	|  |
		--- X --+--X --- output





3. rgster
		       |       |
	       ---+-+- X ---+- X ---+---- output
		  | | 	    | 	    |
		  | |	    |	    |
		  +-----------------+
		    |	    |
		    |	    |
	       -    +-------+
		|   |
      reset ---	X +-+
				
		




4.


2 clock signals


pass value through first stage			(pass output of logic to registers)

pass value through second stage			(pass output of registers to logic calcs)

next instruction



	+--+    +--+    +--+
	|  |    |  |    |  |		clock A, logic output goes through to registers
	|  |    |  |    |  |
--------+  +----+  +----+  +--



  	    +--+    +--+    +--+
   	    |  |    |  |    |  |	clock B, output of registers goes to logic calcs
	    |  |    |  |    |  |
------------+  +----+  +----+  +--


			

	