

11. full inst. set


	and
	or
	xor
	not

	left shift
	right shift

	load register R1 from memory
	load register R1 from memory address AR

	transfer R1 to R2
	transfer R1 to AR
	transfer R1 to TSH
	transfer R1 to IH

	store to memory

	jump 
	jump on zero
	jump on not zero
	jump on less than zero
	jump on less than or equal to zero
	jump on gt than zero
	jump on gt than or equal to zero

	time slicing on
	time slicing off

	wk cycle finished



optional
	add
	subtract



12.


		R1

		R2

		AR	Address register for load/save

		IP	Instruction address


		TSH	Address of time slice handler routine

		IH	Address of interrupt handler routine
	

		Tx	Data following instruction byte for address, data item, etc.
		
		

Notes

time slicing, saves all registers and jumps to location of time slice handler routine


interrupt, jumps to interrupt handling routine, with interrupt number in register 


wk cycle finished, power to main part of chip is shut down, restarts when an interrupt

	is received (keyboard, data signal etc). to reduce power consumption






