Hardware bus


1.

32 bits control

	control byte from controller
	device number byte from controller

	control byte from device
	device number byte from device


64 bits data/address



controller control bytes

	identify device cap.

		number of bytes read at a time 8,16,32,64
		number of bytes written at a time 8,16,32,64
		max bus speed, in mhz

	data available

	write data if necessary



data written

	to device number
	address

	to device number
	data


devices cpu, other chips, separate boards, external connecter ertc.


2.

lines held high by 100k resistor

taken low by transistor switch on

can have multiple on (clash of different boards) however not the intended operation



3.

switch on

wait 10 ns

process data on the bus address/data lines

switch on new code

etcl;;



4. multiple speeds

	alternatives

	1. allocate 1% of time to a 1mhz speed for other devices
	
	2. switch speeds to the correct speed for that device

	3. constant speed




5. conroller chip

	rotate around each device, reading data from that device across the bus into internal registers

	rotate around all devices, delivering the bytes send from other devices to the destination device

	repeat these two steps, e.g. 10 cycles first step, 10 cycles first second step, repeat


6. some method needed to allocate device numbers to each device







